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3 v/5 v, rail-to-rail quad, 8-bit dac ad7304/ad7305 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures four 8-bit d a c s in one package +3 v, +5 v, an d 5 v o p eratio n rail-to-rail r e f input to voltag e output swing 2.6 mhz refere nce multiplyin g bandwidth internal power-on reset spi serial int e rf ace-compatibl e ad7304 fast paralle l in terfacead7 3 05 40 a power sh utdown applic ati o ns automotive output span volta g e instrumentation, digitally controlled calibrat ion pin-compatible ad7 226 r e placement when v dd < 5.5 v gener a l description the ad7304 /ad7305 1 a r e q u ad , 8- b i t d a cs t h a t o p er a t e f r o m a sin g le +3 v t o +5 v s u p p l y , o r 5 v s u p p lies. the ad7304 has a s e r i al in t e r f ac e , whil e t h e ad7305 has a p a ral l e l in t e r f ac e . i n t e rn al p r eci s i o n b u f f e r s sw in g ra il- t o- ra il . th e r e f e r e n c e in p u t ra n g e i n cl u d e s b o t h s u p p l y rai l s, al l o w i ng fo r p o s i t i ve o r neg a t i ve f u l l -s cale o u t p ut v o l t a g es. o p era t io n is g u a r a n te e d o v er t h e s u p p l y v o l t a g e r a n g e o f 2.7 v t o 5.5 v , co n s u m in g les s than 9 mw f r o m a 3 v s u p p l y . the f u l l -s c a le vol t a g e o u t p u t is det e r m i n e d b y t h e ext e r n al r e f e r e n c e in p u t v o l t a g e a p p l i e d . t h e ra il- t o- ra il v ref in p u t t o da c v ou t al lo ws f o r a f u l l -s ca le v o l t a g e s e t e q ual t o t h e p o si tiv e su p p ly , v dd , th e n e ga ti v e s u p p l y , v ss , o r a n y val u e in be tw e e n . the ad7304 s do u b led-b u f f er ed s e r i al da t a in t e r f ace o f f e rs hig h s p ee d , 3-wir e , s p i?-, an d micr o c o n tr ol ler - co m p a t i b l e in p u ts usin g da ta in (s d i ), c l o c k (clk), a n d chi p s e lec t ( cs ) p i n s . a d d i t i on a l ly , a n i n te r n a l p o we r - on re s e t s e t s t h e output to z e ro sc al e . the p a ral l e l in p u t ad7305 us es a s t anda r d addr es s deco de a l o n g w i th th e wr co n t r o l line t o l o ad da t a in t o t h e in p u t re g i ste r s . the dou b le-b uf f e r e d a r c h i t e c t u r e al lo ws al l f o ur in p u t r e g i s t ers to b e p r elo a de d wi t h ne w v a l u es , fol l o w e d b y a n ld a c co n t r o l s t r o be tha t co p i e s all th e n e w da ta i n t o th e d a c r e gi s t e r s, t h er e b y u p da t i ng t h e analog o u t p u t val u es. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___ __ __ __ __ __ __ __ __ __ __ __ __ _ 1 p r ot ec t e d under p a t e n t no . 5684481. func ti on a l bl ock di a g r a ms cs pwr-on reset v ss ad7304 v out a input reg a dac a ldac sdi/shdn gnd clk 8 8 8 8 dac a reg dac b 8 8 8 8 8 dac d dac c serial reg v ref b v ref a clr v ref cv ref d v dd v out b v out c v out d input reg b dac b reg input reg c dac c reg input reg d dac d reg 01114-001 fi g u r e 1 . pwr-on reset ad7305 v out a input reg a dac a ldac 8 8 8 8 dac a reg dac b 8 8 8 8 8 dac d dac c decode v ref v ss gnd v dd v out b v out c v out d input reg b dac b reg input reg c dac c reg input reg d dac d reg 01114-002 db0 db1 db2 db3 db4 db5 db6 8 wr a 0/shdn a1 fi g u r e 2 . w h en op era t ing f r o m les s tha n 5.5 v , t h e ad7 305 is p i n-co m p a t ib le wi th t h e p o p u lar ind u s t r y -s tanda r d ad7226. an in t e r n al p o w e r - o n r e s e t p l aces bo t h p a r t s in t h e zer o -s c a le s t at e at t u r n - o n . a 4 0 a p o w e r s h u t d o w n ( s h d n ) f e at u r e i s a c ti v a t e d o n bo t h pa r t s b y th r ee- s t a t i n g th e s d i/ s h d n p i n o n th e ad7304 and thr e e-s t a t in g t h e a0/s hdn addr es s p i n on t h e ad7305. the ad7304 /ad7305 a r e s p ecif ied o v er t h e extended in d u s t r i a l ?40c t o +85c a nd t h e a u t o mo ti v e ?40c t o +125c t e m p era t ur e ra ng es. ad7304s a r e a v a i lab l e in a wide-bo d y 16-lead so i c ( r -16) p a c k a g e . the p a ral l e l in p u t ad7305 is a v a i la b l e i n t h e wi de- b o d y 20-l e ad so i c (r -20 ) s u r f ace- m o u n t pa c k a g e . f o r ul tr a c o m pa ct a p p l ic a t i o n s , th e thi n 1 . 1 m m , 16-lead tsso p (r u-16) p a c k a g e is a v a i lab l e f o r th e ad7304, while t h e 20-lead tsso p (r u-2 0 ) h o us es t h e ad7305.
ad7304/ad7305 rev. c | page 2 of 20 table of contents specifications ..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 10 circuit operation ........................................................................... 14 dac section ................................................................................ 14 ad7304 serial data interface ....................................................... 15 ad7304 hardware shutdown shdn ...................................... 15 ad7304/ad7305 power-on reset .......................................... 15 power up sequence ..................................................................... 15 ad7305 parallel data interface .................................................... 16 ad7226 pin compatibility ....................................................... 16 ad7305 hardware shutdown shdn ...................................... 16 esd protection circuits ............................................................ 16 applications ..................................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 11/04data sheet changed from rev. b to rev. c update format ....................................................................universal update features ................................................................................ 1 changes to figure 35...................................................................... 15 add power-up sequence ............................................................... 15 changes to figure 36...................................................................... 16 change to figure 37 ....................................................................... 16 updated outline dimensions ....................................................... 18 2/04data sheet changed from rev. a to rev. b renumber tpcs and figures ............................................universal deleted n-16 and n-20 packages.....................................universal changes to absolute maximum ratings ....................................... 3 changes to ordering guide ............................................................ 4 updated outline dimensions ....................................................... 14 3/98changed from rev. 0 to rev. a 2/98revision 0: initial version
ad7304/ad7305 rev. c | page 3 of 20 specifications @ v dd = 3 v or 5 v, v ss = 0 v; or v dd = +5 v and v ss = C5 v, v ss v ref v dd , ?40c < t a < +85c/+125c, unless otherwise noted. table 1. parameter symbol condition 3 v 10% 5 v 10% 5 v 10% unit static performance resolution 1 n 8 8 8 bits integral nonlinearity 2 inl 1 1 1 lsb max differential nonlinearity dnl monotonic, all codes 0 to 0xff 1 1 1 lsb max zero-scale error v zse data = 0x00 15 15 15 mv max full-scale voltage error v fse data = 0xff 4 4 4 lsb max full-scale temperature coefficient 3 tcv fs 5 5 5 ppm/c typ 4 reference input v refin range v refin v ss /v dd v ss /v dd v ss /v dd v min/max input resistance (ad7304) r refin code = 0x55 28 28 28 k? typ input resistance (ad7305) r refin all dacs at code = 0x55 7.5 7.5 7.5 k? typ input capacitance 3 c refin 5 5 5 pf typ analog outputs output voltage range v out v ss /v dd v ss /v dd v ss /v dd v min/max output current drive i out code = 0x80, ?v out < 1 lsb 3 3 3 ma typ shutdown resistance r out dac outputs placed in shutdown state 120 120 120 k? typ capacitive load 3 c l no oscillation 200 200 200 pf typ logic inputs logic input low voltage v il 0.6 0.8 0.8 v min logic input high voltage v ih 2.1 2.4 2.4 v max input leakage current 5 i il 10 10 10 a max input capacitance 3 c il 8 8 8 pf max ac characteristics 3 output slew rate sr code = 0x00 to 0xff to 0x00 1/2.7 1/3.6 1.0/3.6 v/s min/typ reference multiplying bw small signal, v ss = C5 v 2.6 mhz typ total harmonic distortion thd v ref = 4 v p-p, v ss = C5 v, f = 1 khz 0.025 % settling time 6 t s to 0.1% of full scale 1.1/2 1.0/2 1.0/2 s typ/max shutdown recovery time t sdr to 0.1% of full scale 2 2 2 s max time to shutdown t sdn 15 15 15 s typ dac glitch q 15 15 15 nvs typ digital feedthrough q 2 2 2 nvs typ feedthrough v out /v ref code = 0x00, v ref = 1 v p-p, f = 100 khz ?65 db supply characteristics positive supply current i dd v logic = 0 v or v dd , no load 6 6 6 ma max negative supply current i ss v ss = C5 v 6 ma max power dissipation p diss v logic = 0 v or v dd , no load 15 30 60 mw max power down i dd_sd sdi/shdn = floating 40 40 40 a typ power supply sensitivity pss ?v dd = 10% 0.004 0.004 0.004 %/% 1 one lsb = v ref /256. 2 the first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operat ion 3 v or 5 v. 3 these parameters are guaranteed by design and not subject to production testing. 4 typical specifications represent av erage readings measured at 25c. 5 the sdi/shdn and a0/shdn pins have a 30 a maximum i il input leakage current. 6 the settling time specification does not apply for negative going transitions within the last three lsbs of ground in single-s upply operation.
ad7304/ad7305 r e v. c | pa ge 4 o f 2 0 v out = 10v p-p +5v 0v ?5 v +5v 0v ?5v (in) v ref = 10v p-p f = 20khz 01114-003 (out) f i gure 3 . ra il -to - r a i l ref e renc e input to o u tput a t 2 0 khz timing spe c ific ations @ v dd = 3 v o r 5 v , v ss = 0 v ; o r v dd = +5 v a nd v ss = C5 v , v ss v ref v dd , C40c < t a < +85c/+125c, u n les s o t h e r w is e n o t e d . table 2. parameter symbol 3 v 10% 5 v 10% 5 v 10% unit interf ace timi ng specific ati o ns 1 , 2 ad7304 only clock width high t ch 70 55 55 ns min clock width low t cl 70 55 55 ns min data setup t ds 50 40 40 ns min data hold t dh 30 20 20 ns min load pulse widt h t ldw 70 60 60 ns min load setup t ld1 40 30 30 ns min load hold t ld2 40 30 30 ns min clear pulse wid t h t clw r 60 60 60 ns min select t css 30 20 20 ns min deselect t csh 60 40 40 ns min ad7305 only data setup t ds 60 40 40 ns min data hold t dh 30 20 20 ns min addres s setup t as 60 40 40 ns min ad d r ess hold t ah 30 20 20 ns min write width t wr 60 50 50 ns min load pulse widt h t ldw 60 50 50 ns min load setup t ls 60 40 40 ns min load hold t lh 30 20 20 ns min 1 the s e parame te rs are guarante e d by d e s i gn and no t subje c t to prod uctio n te s t ing. 2 al l input control s i gnal s are s p ecif ied with t r = t f = 2 ns (1 0% to 90% of v dd ) a n d t i m e d from a vol t a g e lev e l of 1.6 v.
ad7304/ad7305 r e v. c | pa ge 5 o f 2 0 absolute maximum ratings table 3. p a r a m e t e r r a t i n g v dd to gnd ? 0.3 v, +8 v v ss to gnd +0.3 v, ? 8 v v ref x to gnd v ss , v dd logic inputs to gnd ? 0.3 v, v dd + 0.3 v v ou tx to gnd ? 0.3 v, v dd + 0.3 v i ou t short-circuit to gnd 50 ma package power dissip a tion (t j max C t a )/ ja t h ermal resista n ce ja 16-lead soic package (r-16) 73c/w 16-lead tssop package (ru-16) 180c/w 20-lead soic package (r-20) 74c/w 20-lead tssop package (ru-20) 155c/w maximum junction temperature (t j max ) 1 5 0 c operating tem p erature range ? 40c to +85c storage temperature range ? 65c to +150c lead temperature r - 1 6 , r- 2 0 , r u - 1 6 , r u - 2 0 ( v a p o r p h a s e , 6 0 s e c ) 235c r-16, r-20, ru-1 6, ru-20 (infrare d, 15 sec) 220c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n s o f t h is sp e c if ic a t ion is n o t im pli e d . e x p o sur e t o ab s o lute m a x i m u m r a t i ng c o nd it i o ns for e x te nd e d p e r i o d s m a y af fe c t d e v i c e rel i a b i l it y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7304/ad7305 r e v. c | pa ge 6 o f 2 0 sdi clk cs ldac sa si a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 t csh t ld2 t css t ld1 sdi clk clr ldac fs zs v out t ds t dh t cl t ch t ldw t s t clrw t s 1 lsb error band 01114-004 f i g u re 4. a d 73 04 g e ner a l tim i ng d i ag r a m t sdr sdi/shdn i dd t sdn 01114-005 f i g u re 5. a d 73 04 ti ming d i ag r a m zoo m in table 4. ad73 04 control log i c truth table cs 1 cl k 1 ldac cl r 1 serial shift r e gi ster functi on input reg f u nct i on dac regi ster function h x h h no effec t no effec t no effec t l + h h d a ta advanc ed 1 bit no effec t no effec t + l h h n o ef f e ct updated with sr conte n ts 2 no effec t h x l h n o ef f e ct latched with sr conte n ts 2 al l i n put register c o ntents transferred 3 h x h C no effec t loaded w i th 0x0 0 loaded with 0x0 0 h x h + no effect latched with 0 x 0 0 latched with 0 x 0 0 1 + p o si t i ve l o gi c t r a n si t i on ; C ne gative lo gic trans i tio n ; x do nt c a re . 2 on e i n put regi st er recei v es t h e da t a bi t s d 7 Cd 0 d e co de d from t h e sr a d dre s s bi t s (a1, a0 ), wh er e r e g a = (0, 0), b = (0, 1), c = (1, 0), a n d d = (1, 1 ) . 3 ldac is a l e vel - s e ns itive input. table 5. ad73 04 serial input register data fo rmat, data is loaded in ms b-first format msb b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb b0 ad7304 sac sdc a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i f b11 (sa c ), sh u t do w n a l l cha n ne l s s s e t t o l o c lo w al l d a cs a e l ace d n a o w e sh u t do wn o de an d a l l o u t u t o l t a es eco e hh e ss t an c e s d c sh u t do w n d e code d cha n ne l s s e t to lo c lo w on l t h e d a c de co de d a dd e s s ts a and a s lace d n sh u t do w n o de
ad7304/ad7305 r e v. c | pa ge 7 o f 2 0 table 6. ad73 05 control log i c truth table wr 1 a1 a0 ldac 2 input register function dac regist er f u nction l l l h register a loaded with db0 to d b 7 latched with previous contents, no change + l l h register a latched with db0 to db7 latched with previous contents, no change l l h h register b loaded with db0 to d b 7 latched with previous contents, no change + l h h register b latched with db0 to db7 latched with previous contents, no change l h l h register c loaded with db0 to d b 7 latched with previous contents, no change + h l h register c latched with db0 to db7 latched with previous contents, no change l h h h register d loaded with db0 to d b 7 latched with previous contents, no change + h h h register d latched with db0 to db7 latched with previous contents, no change h x x l no effect all input regist er contents lo aded, register transparent l x x l input register x transparent to db0 to db7 register transparent h x x + no effect all input regi ster contents latch e d h x x h no effect, device not sele cted no effect, device not selected 1 + po si t i ve l o gi c t r a n si t i on ; C ne gative lo gic trans i tio n ; x d o nt care . 2 ldac is a l e vel - s e ns itive input. t ah t dh t lh t ldw t wr t as t ds t ls t s 1 lsb error band a0, a1 wr d0?d7 ldac v out 01114-006 f i g u re 6. a d 73 05 g e ner a l tim i ng d i ag r a m t sdr a0/shdn i dd t sdn 01114-007 f i g u re 7. a d 73 05 ti ming d i ag r a m zoo m in
ad7304/ad7305 r e v. c | pa ge 8 o f 2 0 pin conf igurations and f u ncti on descriptions v out b 1 v out a 2 v ss 3 v ref a 4 v out c 16 v out d 15 v dd 14 v ref c 13 v ref b 5 v ref d 12 gnd 6 sdi/shdn 11 ldac 7 clk 10 clr 8 cs 9 ad7304 top view (not to scale) 01114-008 f i g u re 8. a d 73 04 p i n conf ig ur at io n ta ble 7. a d 73 04 pi n f u nct i o n d e s c ri pt i o ns pin no. mnemonic description 1 v ou t b channe l b rail-t o-rail buffered dac voltage output. full-scale set by reference voltage ap plied to v ref b pin. output is open circuit when shdn is enabled. 2 v ou t a channel a rail-to-rail buffered da c voltage output. full-scale set by reference voltage ap plied to v ref a pin. output is open circuit when shdn is enabled. 3 v ss negative power supply input. specifie d range o f operation is 0 v to ? 5.5 v. 4 v ref a channel a reference input. establishes v ou t a full-sca l e vo ltage. specified range of operation i s v ss < v ref a < v dd . 5 v ref b channe l b reference input. establish e s v ou t b ful l -sca le vo ltage. specified range of operation i s v ss < v ref b < v dd . 6 gnd common analog and digital ground. 7 ldac load dac regis t er strobe, active lo w. simultan eously transfers d a ta from all fo ur input registers into the corresponding dac registers. asynchron o us ac tive low input. dac register is transpare n t when ldac = 0. see t a ble 4 for oper a tion. 8 clr clears al l input and dac registers to the zero condition. asyn chronous active low input. the serial register is not effected. 9 cs chip select, acti ve low input. disabl es sh ift register lo ad ing wh en high. t r ansfe r s seria l input register d a ta to the decoded input regis t er w h en cs returns high. does not effect ldac operation. 10 clk clock in put, positive edge clocks data into shift register. disabl ed by chip selec t cs . 11 sdi/shdn serial data inpu t loads directly into the shift re gist er, msb first. hardware shutdown (shdn) c o ntrol in put, active when p i n is left floating b y a three-state logic dr iver. does not effect dac regi ster conten ts as long a s power i s prese n t on v dd . 12 v ref d channe l d reference input. establish e s v ou t d full-sca l e vo ltage. specified range of operation i s v ss < v ref d < v dd . 13 v ref c channe l c reference input. establishes v ou t c ful l -sca le vo ltage. specified range of operation i s v ss v ref c < v dd . 14 v dd positive power supply input. specified ra nge of operation is 2.7 v to 5.5 v. 15 v ou t d channel d rail-to-rail buffered da c voltage output. full-scale set by reference voltage ap plied to v ref d pin. output is open circuit when shdn is enabled. 16 v ou t c channe l c rail-to-rail buffered dac voltage output. full-scale set by reference voltage ap plied to v ref c pin. output is open circuit when shdn is enabled.
ad7304/ad7305 r e v. c | pa ge 9 o f 2 0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v out a v ss v ref db7 ldac gnd v out b v out d v dd a0/shdn db0 wr a1 db4 db5 db6 db3 db2 db1 v out c ad7305 top view (not to scale) 01114-009 f i g u re 9. a d 73 05 p i n conf ig ur at io n ta ble 8. a d 73 05 pi n f u nct i o n d e s c ri pt i o n pin o. mnemonic description 1 v ou t b channe l b rail-t o-rail buffered dac voltage output. full-scale set by reference voltage ap plied to v ref b pin. output is open circuit when shdn is enabled. 2 v ou t a channel a rail-to-rail buffered da c voltage output. full-scale set by reference voltage ap plied to v ref a pin. output is open circuit when shdn is enabled. 3 v ss negative power supply input. specified ra nge of operation is 0 v to C5.5 v. 4 v ref channel b reference input. establishes v ou t full-scale v o ltage. s p ecified range o f operation is v ss < v ref < v dd . 5 gnd common analog and digital ground. 6 ldac load dac regis t er strobe, active low. simultan eously transfers d a ta from all fo ur input registers into the corresponding dac registers. asynchron o us ac tive low input. dac register is transpare n t when ldac = 0. see table 6 for operation . 7 db7 msb digital input data bit. 8 db6 data bit 6. 9 db5 data bit 5. 10 db4 data bit 4. 11 db3 data bit 3. 12 db2 data bit 2. 13 db1 data bit 1. 14 db0 lsb digital input data bit. 15 wr write data into input register c o ntrol li ne, acti ve low. see tab l e 6 for operatio n . 16 a1 address bit 1. 17 a0/shdn address bit 0/hardware shutdown (shdn) cont rol input, active when pin is le ft floating by a three-state logic driver. does not effect dac regi ster cont ents as long as p o wer i s present on v dd . 18 v dd positive power supply input. specified ra nge of operation is 2.7 v to 5.5 v. 19 v ou t d channel d rail-to-rail buffered da c voltage output. full-scale set by reference voltage ap plied to v ref d pin. output is open circuit when shdn is enabled. 20 v ou t c channe l c rail-to-rail buffered dac voltage output. full-scale set by reference voltage ap plied to v ref c pin. output is open circuit when shdn is enabled.
ad7304/ad7305 rev. c | page 10 of 20 typical perf orm ance cha r acte ristics v out (mv) 144 120 0 01 5 reference input voltage (v) 1.0 0.6 ?1.0 ?5.0 5.0 ? 3.0 inl ( l sb) ?1.0 1.0 3.0 0.2 ?0.2 ?0.6 v dd = +5v v ss = ? 5v data = 0x80 t a = +25 c dac a dac b dac c dac d 01114-013 3 i out s i nk curre nt (ma) 69 1 2 96 72 48 24 v dd = +5v v ss = ? 5v v ref = v dd data = 0x00 01114-010 f i g u re 10. i ou t sink vs. v ou t ra il-t o -r ai l p e r f o r m a nce v out output voltage (v) ?35 ?28 0 4.0 5.0 4.2 i out s o urce curre nt (ma) 4.4 4.6 4.8 ?21 ?14 ?7 v dd = +5v v ss = ? 5v v ref = v dd data = 0xff 01114-011 f i g u re 11. i ou t sou r ce vs. v ou t ra il -t o - r a il p e r f or ma nc e code (decimal) +1 0 0 256 32 inl ( l sb) 64 96 128 160 192 224 0 0 +1 ?1 +1 ?1 +1 ?1 0 ?1 dac a dac b dac c dac d v dd = +5v v ss = ? 5v v ref = +2.5v t a = +25 c 01114-012 f i gure 12. inl vs. code , all d a c c h an nels f i gure 13. inl v s . r e ferenc e input v o lt age code (decimal) 0.500 ? 0.500 0 256 32 dnl (ls b ) 64 96 128 160 192 224 0.375 0 ? 0.125 ? 0.250 ? 0.375 0.250 0.125 v dd = +5v v ss = ? 5v v ref = +2.5v 01114-014 f i g u re 14. dnl v s . code temperature ( c) 4.0 3.6 2.0 ?55 125 ?35 zer o - s c a l e volta ge ( m v) ?15 5 25 45 65 85 105 3.2 2.8 2.4 v dd = 5.5v v ss = 0v v ref = 5.45v 01114-015 f i gure 15. zero -s c a le v o ltag e v s . t e mper atu r e
ad7304/ad7305 rev. c | page 11 of 20 cs 5v 0v 0v v out 01114-016 v dd = 5v v ref = 4v data = 0x00 0xff 2 s/div f i gure 1 6 . la r g e-s i gna l s e ttli n g t i m e v out a ? 5v 0v +5v ? 5v 0v +5v v refin ( 5v @ 50khz) data = 0xff 01114-017 2 s/div f i g u re 17. m u lt ip ly i n g m o de step r e s p ons e and o u t p ut s l ew r a te frequency (hz) 6 ?8 10k 10m gain ( d b) 4 1m 100k 0 ?4 ?6 v dd = +5v v ss = ? 5v data = 0xff v ref = 100mv rms f ?3db = 2.6mhz 01114-018 f i g u re 18. m u lt ip ly i n g m o de g a in v s . f r equ e nc y v out cs r l = 10k ? r l = 70k ? no load v dd = 5v c l = 150pf 01114-019 5 s/div f i g u re 19. ti m e t o s h utd o wn cs v out i dd 1ma/v v dd = 5v 01114-020 f i gure 20. sh u t do w n rec o ver y t i m e ( w akeup) v ref amplitude (v p-p) 10 1 0.001 10m 10 1 thd (%) 23 4 5 6 7 8 9 0.1 0.01 v dd = +5v v ss = ? 5v 01114-021 f i gure 21. thd vs . refer e n c e i n put a m plitude
ad7304/ad7305 rev. c | page 12 of 20 frequency (hz) 1 0.1 0.001 20 100k 100 thd (%) 1k 10k 0.01 v dd = +5v v ss = ? 5v 01114-022 f i g u re 22. th d v s . f r equ e nc y 3.0 2.4 0 1 100k 10 nois e de ns ity ( v/ h z ) 100 1k 10k 1.8 1.2 0.6 v dd = +5v v ss = ? 5v v ref = +4v data = 0xff frequency (hz) 01114-023 f i g u re 23. o u t p ut nois e v o lt ag e d e ns it y v s . f r eq uenc y 50ns/div clk v dd = +5v v ss = ? 5v v ref = +2.5v dac a = 0xff dac b = 0x00 f = 2mhz v out b 01114-024 50ns/div f i gure 2 4 . di g i ta l f eedthro u g h cs v dd = +5v v ss = ? 5v v ref = +2.5v f = 1mhz data = 0x80 0x7f v out 01114-025 f i g u re 25. m i ds c a l e t r ans i t i on g l itch frequency (hz) 40 20 ? 160 100 10m 1k cros s talk (db) 10k 1m 0 ?2 0 ?4 0 v dd = +5v v ss = ? 5v v ref = 50mv rms dac a data = 0xff dac b, dac c, dac d data = 0x00 ?6 0 ?8 0 ? 100 ? 120 ? 140 v out b v ref ct = 20 log 100k 01114-026 fi g u r e 2 6 . c r o s s t a l k v s . fr e q u e n c y frequency (hz) 60 0 10 100 p s rr (db) 1k 100k 50 40 30 20 10 10k data = 0x80 t a = +25 c +psrr, v dd = +5v ? 10% ?psrr, v ss = ? 5v ? 10% +psrr, v dd = +3v ? 10% ? psrr, v ss = ? 3v ? 10% 01114-027 f i gure 27. p o wer - s u p p ly rej e c t ion vs. f r equ e nc y
ad7304/ad7305 rev. c | page 13 of 20 digital input voltage (v) 12 10 0 05 1 s u p p l y curre nt (ma) 23 4 8 6 4 2 v dd = +5v v ss = ? 5v v ref = +2.5v a0 = +5v all other digital pins varying i dd i ss 01114-028 f i gure 28. sup p l y current v s . d i gita l i n put v o ltag e digital input voltage (v) 10 1 0.0001 05 1 s u p p l y curre nt (ma) 234 0.1 0.01 0.001 v dd = +5v v ss = ? 5v v ref = +2.5v all digital pins vary, except a0 = +5v i dd i ss 01114-029 f i g u re 29. shu t do w n sup p l y cur r ent v s . d i g i t a l input v o lt ag e (a 0 o n ly ) temperature ( c) 5.0 4.4 2.0 ? 5 5 125 ?35 s u p p l y curre nt (ma) ? 1 5 5 25 45 65 85 105 3.8 3.2 2.6 v dd = +5v v ss = ? 5v v ref = +2.5v i dd and i ss 01114-030 f i gure 30. sup p l y current v s . t e mper at ur e 80 20 ?55 125 ?35 sh u t d o w n su pply ( a) ? 1 5 5 25 45 65 85 105 70 60 50 40 30 v dd = +5.5v v ss = ? 5.5v v ref = +2.5v pin a0 floating temperature ( c) 01114-031 f i gure 31. sh u t do w n sup p l y c u r r ent vs. t e mp e r atu r e temperature ( c) 0.08 ? 0.04 08 4 normalize d total unadj us te d e rror drift (ls b ) 168 252 336 420 504 0.04 0 ? 0.08 reading made at t a = +25 c sample size = 924 units v dd = +2.7v v dd = +5.5v 01114-032 f i gur e 3 2 . norm al iz e d tue dr i f t a c c e le r a t e d b y bur n -in ho ur s of o p er at i o n @ 1 5 0 c
ad7304/ad7305 rev. c | page 14 of 20 circuit ope ration the ad7304 /ad7305 a r e 4-c h a nne l , 8-b i t, v o l t a g e o u t p u t d a cs, dif f er in g p r ima r i l y in d i g i t a l log i c i n t e r f ace an d n u m b er o f r e fer e n c e in pu ts. b o t h p a r t s sha r e t h e s a m e i n t e r n al d a c d e si g n a n d tr u e ra il-t o- ra il o u t p u t b u f f e r s. th e a d 7 3 0 4 co n t a i n s f o ur i n d e pen d en t m u l t i p l y in g r e f e r e n c e in p u t s , wh ile t h e ad7305 has one co mm o n r e f e r e n c e in p u t. th e ad7304 us es a 3-wir e s p i-co m p a t i b l e s e r i al da ta in t e r f ac e , w h i l e the ad7305 of fe rs an 8 - b i t p a r a l l el da t a i n te r f ac e. dac section e a c h p a r t co n t ain s f o ur v o l t a g e-swi t ch e d r - 2r ladder d a cs . f i gur e 33 sh o w s a typ i cal eq u i va len t d a c. th es e d a cs a r e d e s i gn ed t o o p era t e bo th si n g l e - s u p p l y o r d u al -s u p p l y , dep e ndi n g o n w h et h e r t h e us er s u p p lies a nega t i v e v o l t a g e on th e v ss p i n. i n a s i ng l e - s u p ply a p pl ic a t ion, t h e v ss is t i e d t o gr o u n d . i n ei t h er m o de , t h e d a c o u t p u t v o l t a g e i s d e t e rmin e d by t h e v ref i n p u t vol t a g e and t h e dig i t a l d a t a (d ) lo ade d in to t h e co r r es p o ndi n g d a c r e g i s t e r acco r d in g t o e q ua t i o n 1. v ou t = v ref d /2 5 6 ( 1 ) n o t e t h a t t h e ou t p ut f u l l -s c a le p o la r i ty is t h e s a m e as t h e v ref p o l a r i ty fo r dc r e fer e nc e vol t ages. v ref db7 2r v dd v ss v out r 2r db6 2r db0 2r 01114-033 f i gure 33. t y pic a l equiv a lent d a c ch annel t h ese d a c s a r e al so d e s i gn e d t o a cco m m o d a t e a c r e f e r e n c e in p u t sig n als. a s lo n g as the ac sig n als a r e ma in ta in e d be tw e e n v ss < v ref < v dd , t h e us er can e x p e c t 50 kh z o f f u l l p o w e r , m u lt i p ly i n g b a n d w i dt h p e r f or manc e. in ord e r t o u s e ne g a t i ve in p u t r e fer e n c e v o l t a g es, t h e v ss p i n m u s t be b i ased w i th a n e ga ti v e v o l t a g e o f eq ual o r gr ea t e r m a gni t ud e t h a n t h e re f e re nc e vo lt ag e. the r e fer e n c e i n p u ts a r e c o de dep e nden t , exhib i t i n g w o rs t - cas e mini m u m r e sist a n ce va l u es sp e c if ie d i n t h e p a r a m e t r ic sp e c if i- ca ti o n ta b l e . t h e d a c o u t p u t s v ou t a, v ou t b, v ou t c, and v ou t d a r e each ca p a b l e o f d r i v in g 2 k? l o ads in pa ral l e l wi t h u p t o 500 pf lo ads. o u t p u t s i n k c u r r en t and s o ur ce c u r r en t ar e sh o w n i n f i gur e 10 an d f i gur e 11, r e s p ec ti v e l y . th e o u t p u t s l e w ra te is n o minal l y 3.6 v / s w h i l e o p era t in g f r o m 5 v s u p p lies. the lo w o u t p u t i m p e dan c e o f t h e b u f f ers minimize s cr os s t al k betw een a n alog in p u t c h a n ne ls. a t 100 kh z, 65 db o f c h a n n e l - t o -cha n n e l is ol a t io n exists (f igu r e 26). o u t p u t vol t a g e n o is e is pl otte d i n f i g u r e 2 3 . i n ord e r to m a i n t a i n go o d an a l o g p e r f or m- a n c e , p o w e r su p p l y b y p a s s in g o f 0.01 f in p a ral l e l wi t h 1 f is r e commende d . the tr ue r a i l -t o - rail c a p a b i l i ty o f t h e ad730 4/ad7 3 0 5 al lo ws t h e us er to co nn e c t t h e r e fer e n c e i n p u ts dir e c t l y t o t h e s a me su p p ly as t h e v dd or v ss p i n (f igur e 34). u n der t h es e co ndi t i on s, cle a n p o w e r su p p ly vol t a g es (lo w r i p p le, a v o i d s w i t c h i n g s u p p l i e s ) ap p r o p r i at e f o r t h e ap p l i c at i o n s h o u l d b e us ed . v dd v ss v out x 120k ? q1 q2 01114-034 f i gure 34. equiv a le nt d a c a m p lifier o u tput cir c uit
ad7304/ad7305 rev. c | page 15 of 20 ad7304 serial data interface the ad7304 us es a 3-wir e ( cs , s d i, clk) s p i - c o m p a t i b le se ri al da t a in t e r f a c e . n e w se r i al da ta i s c l oc k e d i n t o t h e se r i al in p u t r e g i st er i n a 12-b i t da t a -wo r d fo r m a t . ms b b i ts a r e lo ade d fi r s t . t a b l e 5 def i n e s t h e 12 da ta-w o r d b i ts. d a t a is p l aced o n the s d i/s h dn pi n a nd clo c k e d in to t h e r e g i ster o n t h e p o si t i ve c l o c k ed g e o f clk s u b j ect t o t h e da t a set u p a n d da ta h o ld t i m e r e q u ir emen t s sp e c if ie d i n t h e t i min g s p e c if ica t i o n s s e c t ion. d a t a can o n ly b e clo c k e d i n w h i l e t h e cs chi p s e l e c t p i n is ac t i ve l o w . o n ly t h e l a st 1 2 -bi t s cl o c ke d i n to t h e s e r i a l re g i ste r a r e in t e r r oga t e d w h en t h e cs p i n r e t u rn s t o th e l o gi c h i gh s t a t e , ext r a da t a b i ts ar e ig n o r e d. si n c e m o s t micr o c on t r ol lers o u t p u t s e r i a l da t a i n 8- b i t b y t e s, tw o r i g h t- j u st if ie d da t a b y t e s ca n b e wr i t t e n t o t h e ad7304. k eep in g th e cs lin e lo w b e tw e e n t h e f i rs t a nd s e cond b y t e tra n sfer r e s u l t s in a s u c c essf u l s e r i al re g i ste r up d a te. on ce t h e da t a is p r o p erl y alig ne d i n t h e shif t r e g i s t er , t h e posi ti v e e d g e o f th e cs ini t ia t e s ei t h er t h e t r a n sfer o f n e w da t a to t h e t a rget d a c r e g i ster , de ter m i n e d b y t h e de co di n g o f a ddr ess bi ts a1 a nd a0, o r t h e sh utdo w n fe a t u r es is ac t i va te d b a s e d on t h e sa c o r s d c b i ts. w h en ei t h er sa c o r s d c p i n s a r e s e t (l o g ic 0) , t h e lo a d in g o f ne w da t a deter m i n e d b y bi ts b 9 t o b0 a r e s t i l l lo ade d , b u t t h e r e s u l t s do n o t a p p e a r o n t h e b u f f er output s u n t i l t h e d e v i c e i s brou g h t out of t h e shutd o w n st a t e. the s e le c t e d d a c o u t p ut v o l t ag es b e com e hig h i m p e dan c e w i t h a n o mina l r e sis t a n ce o f 120 k? t o g r o u n d , s e e f i gur e 34. i f b o t h t h e s a c a n d sd c pi ns are s e t , a l l ch an n e l s are st i l l pl a c e d in sh u t do wn mo de . w h en t h e ad7304 has be en p r og ra mm e d in t o t h e p o w e r sh u t do wn st a t e , t h e p r es e n t d a c r e g i s t er da t a is ma in t a i n e d as l o n g as v dd r e m a in s g r ea t e r than 2.7 v . th e r e ma ini n g cha r ac t e r i st ics o f t h e s o f t w a r e s e r i a l in t e r f a c e a r e def i n e d b y t a b l e 4, t a b l e 5, and f i gur e 5. t w o ad di ti o n al p i n s , clr a nd ld a c , o n t h e ad7304 p r o v ide h a rdw a re c o n t r o l o v e r t h e cl e a r f u nc t i o n a n d t h e d a c re g i s t e r lo ading. i f t h es e f u n c t i o n s a r e no t n e e d e d , t h e clr p i n c a n b e ti ed t o logi c h i g h , a n d t h e ld a c p i n c a n b e t i e d to lo g i c lo w . the asy n chr o n o us in p u t clr p i n fo r c es a l l in p u t and d a c r e g i s t ers t o t h e zer o -co d e s t a t e. the asy n chr o n o us ld a c pi n ca n be str o be d t o a c ti v e lo w w h e n all d a c r e gis t e r s n eed t o be u p da te d s i m u l t ane o u sly f r om t h e i r re sp e c t i ve in p u t re g i ste r s . the ld a c p i n places t h e d a c r e g i s t e r in a t r a n s p a r en t m o de while in t h e log i c lo w s t a t e . ad7304 dac a dac a b c d 2:4 decode a0 a1 sdc sac d0 d1 d2 d3 d4 d5 d6 d7 8 en 320k ? 280k ? 80k ? 640k ? 680k ? v dd ldac v ss v out c cs sdi v out b v out a v dd dq input register r power- on reset v ref a v ref b v ref c v ref d v out d clr gnd clk input register r r r dq dq dq oe dac a register dac b oe dac b register dac c oe dac c register dac d oe dac d register 01114-035 input register input register r r r r f i gur e 3 5 . ad73 04 e q ui v a le nt l o gic int e r f ac e ad7304 hardware shutdown shdn i f a t h r e e - s t a t e dr i v er is us e d on t h e s d i/ s h dn p i n, t h e ad7304 can be p l aced in t o a p o w e r s h u t do wn m o de w h en t h e s d i/ s h d n p i n is p l aced in a hig h im p e dan c e sta t e. f o r p r o p er op e r a t i o n , no ot he r te r m i n a t i o n vo lt age s s h ou l d b e pre s e n t on this p i n. an in ter n al win d o w c o m p a r a t o r det e c t s w h en t h e log i c vol t a g e o n t h e shdn p i n is b e t w e e n 28 % an d 3 6 % o f v dd . a hig h im p e dan c e in t e r n a l b i as ge n e ra t o r p r o v i d e s t h is v o l t a g e on t h e s h d n pin. the fo ur d a c o u t p ut v o l t a g es b e com e hig h im p e dan c e wi th a n o minal r e sista n c e o f 120 k? t o g r o u n d (s e e f i gur e 34 f o r a n eq uivalen t circ ui t). ad7304/ad7305 power-on reset w h en t h e v dd p o we r su p p ly is t u r n e d on , an in te r n a l re s e t st ro b e f o rc e s a l l t h e i n put a n d d a c re g i st e r s t o t h e z e ro - c o d e st a t e. t h e v dd p o we r su p p ly s h ou l d ha ve a monotonic a l l y in cr eas i n g ra m p in o r der t o ha ve co n s is t e n t r e su l t s, es p e c i al l y in t h e r e g i on of v dd = 1.5 v t o 2.3 v . th e v ss s u p p ly has n o ef f e c t o n t h e p o w e r - on r e s e t p e r f o r m a n c e . th e d a c r e g i s t er da t a st a y s at z e ro u n t i l a v a l i d s e r i a l re g i ste r s o f t w a re l o a d t a ke s p l ace . i n t h e cas e o f th e do u b l e -b uf f e r e d ad730 5, th e ou t p u t d a c re g i ste r c a n on ly b e c h ang e d onc e t h e ld a c st rob e is ini t i a t e d . power-up sequence i t is r e co mm e nde d to p o w e r v dd /v ss f i r s t bef o r e a p p l yi n g a n y volt age to t h e re fe re nc e te r m i n a l s to a v oi d p o te n t i a l l a tc h up . the id e a l p o w e r - u p s e q u e n c e is in t h e fol l o w in g o r der : gnd , v dd , v ss , dig i t a l i n p u ts, an d v re fx . t h e ord e r of p o we r i ng dig i t a l i n p u ts and r e fer e n c e i n pu ts is n o t i m p o r t a n t as lo n g as t h e y are p o we re d af te r v dd /v ss .
ad7304/ad7305 rev. c | page 16 of 20 ad7305 parallel data interface the ad7305 has a n 8-b i t p a ral l e l in t e r f ac e d b 7 = ms b , d b 0 = ls b . t w o ad dr e s s b i ts, a1 and a0, a r e de co de d w h en an ac t i ve lo w wr i t e st r o b e is place d on t h e wr p i n, s e e t a b l e 6. the wr is a le vel-s e n s i t ive in p u t p i n, t h er efo r e, t h e da t a s e t u p and d a t a h o ld t i m e s def i n e d i n t h e t i mi n g s p e c if ic a t io ns s e c t io n n e e d to be ad h e r e d t o . ad7305 8 320k ? 280k ? 80k ? 640k ? 680k ? v dd ldac v ss wr v dd v ref gnd data db0?db7 a1 a0/shdn r r r r power- on reset dac a oe dac a register dac b oe dac b register dac c oe dac c register dac d oe dac d register dac a b c d 2:4 decode v out c v out b v out a v out d 01114-036 input register input register input register input register r r r r f i gur e 3 6 . ad73 05 e q ui v a le nt l o gic int e r f ac e the ld a c pi n prov i d e s t h e c a p a bi l i t y of s i m u lt a n e o u s l y u p d a ti n g a l l d a c r e gi s t e r s w i th n e w d a t a fr o m t h e i n p u t r e g i s t ers a t the s a m e t i m e . this r e s u l t s in the a n alog o u t p u t s al l ch ang i ng to t h e i r ne w v a lu e s a t t h e s a m e t i me . t h e ld a c pi n i s a le ve l-s e n s i t i v e in p u t. i f t h e sim u l t an e o us u p da t e f e a t ur e is no t re qu i r e d , t h e ld a c p i n can b e t i e d to lo g i c lo w . w h e n t h e ld a c i s ti ed t o logi c lo w , t h e d a c r e gi s t e r s bec o m e t r a n s p a r en t and t h e in p u t r e g i ster da t a det e r m i n es t h e d a c o u t p u t v o l t a g e (see f i gur e 36 f o r a n eq ui val e n t in t e rfa c e l o gi c di a g ra m ) . ad7226 pin compatibility by ty ing t h e ld a c p i n t o g r o u nd , t h e ad7305 has t h e s a me p i n co nf igura t io n and f u n c tio n al i t y as th e ad7226, wi th t h e e x c e pt i o n of a l o we r p o we r supply op e r a t i n g v o lt age. ad7305 hardware shutdown shdn i f a thr ee-s t a t e dr i v er is us ed on t h e a0 /s hdn p i n, t h e ad7 305 c a n be p l a c ed in t o a po w e r s h u t d o wn m o de wh e n th e a 0 /s hd n p i n is pl ace d in a hig h i m p e dance st a t e. f o r p r o p er o p er a t ion, no ot he r te r m i n a t i o n vo lt age s s h ou l d b e pre s e n t on t h i s pi n . a n in t e r n al wi n d o w co m p a r a t o r det e c t s w h en t h e log i c v o l t a g e o n t h e s h dn pin i s b e tw e e n 28 % a nd 36% o f v dd . a hig h im p e d- anc e , i n te r n a l - b i a s ge ne r a tor pro v i d e s t h i s volt a g e on t h e sh d n p i n. th e fo ur d a c o u t p ut v o l t ag es b e com e hig h i m p e dan c e wi th a n o minal r e sis t a n ce o f 12 0 k? t o g r o u nd . esd protection circuits al l log i c in p u t p i n s co n t a i n back-b ias e d es d p r o t e c tio n z e n e rs co nn e c te d to g r o u nd (gn d ). t h e v ref p i n s als o co n t a i n a back- bi a s e d e s d prot e c t i on z e ne r c o n n e c te d to v dd (s ee f i gur e 37). gnd digita l inputs v dd v ref x 01114-037 f i gure 37. equiv a le nt e s d p r ote c tio n c i rcuits
ad7304/ad7305 rev. c | page 17 of 20 appli c ations the ad7304 /ad7305 a r e in h e ren t l y 2-q u adra n t m u l t i p l y in g d a cs. tha t is , t h e y ca n e a sil y b e s e t u p fo r uni p ola r o u t p u t o p era t ion. th e f u l l -s cale ou t p u t p o la r i ty is t h e s a m e as t h e re f e re nc e i n put vo lt age p o l a r i t y . i n s o m e a p pl i c a t i o ns , i t m a y b e ne c e s s ar y to ge ne r a te t h e f u l l 4 - qu a d r a n t m u lt i p ly ing c a p a b i l i ty or a b i p o l a r ou t p ut s w ing . this is easil y ac co m p lish e d usin g a n ext e r n al t r ue ra il-t o-ra il o p a m p , s u ch as t h e o p 295. c o nnec tin g t h e ext e r n al a m p l if ier wi th t w o e q u a l v a lu e re s i stor s , a s show n i n f i g u re 3 8 , re su lt s i n a f u l l 4-q u a d ra n t m u lt i p ly in g c i r c ui t. i n t h i s cir c ui t, t h e am plif ier p r o v ide s a ga i n o f tw o , w h ich i n cr e a s e s t h e o u t p u t sp a n ma g n i t u d e t o 1 0 v . th e tra n sf er eq ua tion o f this cir c ui t sho w s t h a t b o th n e g a ti v e a n d po s i ti v e o u t p u t v o l t a g e s a r e c r e a t e d a s t h e in p u t d a t a ( d ) is in cr e m e n te d f r o m co de ze r o (v ou t = C5 v) to mi ds c a l e ( v out = 0 v) t o f u l l s c ale (v ou t = +5 v). ref out v d v ? = 1 128 ( 2 ) +5v 10k ? ? < < f i g u re 38. 4- q u adr a nt m u lt iply ing a p plic at i o n c i rcu i t
ad7304/ad7305 rev. c | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013aa seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 16 9 8 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) coplanarity 0.10 f i g u re 39. 16-l ead standar d s m all o u tline p a ck age [s oi c ] w i de body (r - 1 6) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ac 0.75 (0.0295) 0.25 (0.0098) 20 11 10 1 8 0 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) bsc 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) coplanarity 0.10 f i gure 40. 20-l ead standar d s m all o u tline p a ck age [s oi c ] w i de body (r - 2 0) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s) 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab f i gure 41. 1 6 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 16) di me nsio ns sho w n i n mi ll im e t e r s 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 f i gure 42. 2 0 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 20) di me nsio ns sho w n i n mi ll im e t e r s
ad7304/ad7305 rev. c | page 19 of 20 ordering guide model temperature range package description package options ad7304br C40c to +85c 16-lead soic r-16 ad7304br-reel C40c to +85c 16-lead soic r-16 ad7304brz 1 C40c to +85c 16-lead soic r-16 ad7304brz-reel 1 C40c to +85c 16-lead soic r-16 ad7304yr C40c to +125c 16-lead soic r-16 ad7304yrz 1 C40c to +125c 16-lead soic r-16 ad7304bru C40c to +85c 16-lead tssop ru-16 ad7304bru-reel7 C40c to +85c 16-lead tssop ru-16 ad7305br C40c to +85c 20-lead soic r-20 ad7305br-reel C40c to +85c 20-lead soic r-20 ad7305yr C40c to +125c 20-lead soic r-20 AD7305YR-REEL C40c to +125c 20-lead soic r-20 ad7305bru C40c to +85c 20-lead tssop ru-20 ad7305bru-reel7 C40c to +85c 20-lead tssop ru-20 ad7305bruz 1 C40c to +85c 20-lead tssop ru-20 ad7305bruz-reel7 1 C40c to +85c 20-lead tssop ru-20 1 z = pb-free part.
ad7304/ad7305 rev. c | page 20 of 20 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . prin ted in th e u.s . a. c01114-0-11/04( c)

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